软件：Vivado2017.4 板卡：Ego1 型号：xc7a35tcsg324-1
四、有限状态机
Moore状态机
只与当前状态有关而与输入无关
`timescale 1ns / 1ps
module seqdetea(input wire clk,input wire clr,input wire din,output reg dout);reg[2:0]present_state,next_state;parameter S0=3'b000,S1=3'b001,S2=3'b010,S3=3'b011,S4=3'b100;//状态寄存器always@(posedge clk or posedge clr)beginif(clr == 1)present_state <=S0;elsepresent_state <=next_state;end//C1模块always@(*)begincase(present_state)S0:if(din == 1)next_state <= S1;elsenext_state <= S0;S1:if(din == 1)next_state <= S2;elsenext_state <= S0; S2:if(din == 1)next_state <= S2;elsenext_state <= S3; S3:if(din == 1)next_state <= S4;elsenext_state <= S0;S4:if(din == 1)next_state <= S2;elsenext_state <= S0;default: next_state <= S0;endcase end //C2模块always@(*)beginif(present_state == S4)dout =1;elsedout = 0;end
endmodule
书写:Test_beach
`timescale 1ns / 1ps
module Moore_tb();
reg clk,clr;
reg din;
wire dout;
seqdetea u0(.clk(clk),.clr(clr),.din(din),.dout(dout));
initial begin
clk = 1'b0;
clr = 1'b0;
end
always begin#50 din = 1'b1;#50 din = 1'b1;#50 din = 1'b0;#50 din = 1'b1;#50 din = 1'b1;#50 din = 1'b0;#50 din = 1'b1;#50 din = 1'b1;#50 din = 1'b0;#50 din = 1'b1;#50 din = 1'b0;#50 din = 1'b0;#50 din = 1'b1;#50 din = 1'b0;#50 din = 1'b0;#50 din = 1'b1;#50 din = 1'b0;#50 din = 1'b1;#50 din = 1'b0;endalways beginclk = 1'b0;#30 clk = 1'b1;#30;end
endmodule
仿真结果：
Mealy状态机
不仅和当前状态有关而且和输入状态也有关
`timescale 1ns / 1ps
module seqdetb(input wire clk,input wire clr,input wire din,output reg dout);reg[1:0]present_state,next_state;parameter S0 = 3'b00,S1 = 3'b01,S2 = 3'b10,S3 = 3'b11;//状态寄存器always@(posedge clk or posedge clr) beginif(clr == 1)present_state <= S0;elsepresent_state <= next_state;end//C1 模块always@(*)begincase(present_state)S0:if(din == 1)next_state <= S1;elsenext_state <= S0;S1:if(din ==1)next_state <=S2;elsenext_state <=S0;S2:if(din == 0)next_state <=S3;elsenext_state <=S0;S3:if(din == 1)next_state <= S1;elsenext_state <=S0;default:next_state <=S0;endcaseendalways@(posedge clk or posedge clr)beginif(clr == 1)dout <=0;elseif((present_state == S3)&&(din == 1))dout <=1;elsedout <=0;end
endmodule