最近刚学DSP，请问里面的那个CSR寄存器的作用是什么呢，要在什么时候对其进行设置呢？
请各位高手指点指点，多谢了！
------解决方案--------------------------------------------------------
通常，控制状态寄存器的控制部分在主程序开始后就进行初始化设置；状态部分用于需要时进行查询；
具体还要看是哪款芯片。举个TI的2407的DEMO例子，头两行就设置了:
/****************************** MAIN ROUTINE ***************************/
void main(void)
{
/*** Configure the System Control and Status registers ***/
*SCSR1 = 0x00FD;
/*
bit 15 0: reserved
bit 14 0: CLKOUT = CPUCLK
bit 13-12 00: IDLE1 selected for low-power mode
bit 11-9 000: PLL x4 mode
bit 8 0: reserved
bit 7 1: 1 = enable ADC module clock
bit 6 1: 1 = enable SCI module clock
bit 5 1: 1 = enable SPI module clock
bit 4 1: 1 = enable CAN module clock
bit 3 1: 1 = enable EVB module clock
bit 2 1: 1 = enable EVA module clock
bit 1 0: reserved
bit 0 1: clear the ILLADR bit
*/
*SCSR2 = (*SCSR2 | 0x000B) & 0x000F;
/*
bit 15-6 0's: reserved
bit 5 0: do NOT clear the WD OVERRIDE bit
bit 4 0: XMIF_HI-Z, 0=normal mode, 1=Hi-Z'd
bit 3 1: disable the boot ROM, enable the FLASH
bit 2 no change MP/MC* bit reflects state of MP/MC* pin
bit 1-0 11: 11 = SARAM mapped to prog and data
*/
/*** Disable the watchdog timer ***/
*WDCR = 0x00E8;
/*
bits 15-8 0's: reserved
bit 7 1: clear WD flag
bit 6 1: disable the dog
bit 5-3 101: must be written as 101
bit 2-0 000: WDCLK divider = 1
*/
/*** Setup external memory interface for LF2407 EVM ***/
WSGR = 0x0040;
/*
bit 15-11 0's: reserved
bit 10-9 00: bus visibility off
bit 8-6 001: 1 wait-state for I/O space
bit 5-3 000: 0 wait-state for data space
bit 2-0 000: 0 wait state for program space
*/
/*** Setup shared I/O pins ***/
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