我的输入是一个频率可变的方波。然后要求输出是固定脉冲宽度为660us的方波，不管输入频率是多少。我的程序总是会在一段时间过后丢失一个输出，请问这是为什么呢？我的程序如下。
entity top_sensors is
port
(
-- Input ports
reset : in std_logic; --! system clock
clk : in std_logic; --! signal reset
I1 : in std_logic; --! pulse sensor 1
-- Output ports
Top_Tour_T1 : out std_logic --! Top round sensor 1 output is fixed for 660us
);
end entity top_sensors;
-------------------------------------------------------------------------------
--! top_sensors architecture declaration
-------------------------------------------------------------------------------
architecture behavior of top_sensors is
signal cpt1: integer RANGE 0 TO 33000:=0; --! 660us=> 660/0.02us=33000: counter clk FPGA=33000
begin
----------------------------------------------------------------------------
--! @brief generate top round for each sensor
--! @detail each top is fixed for 660us
----------------------------------------------------------------------------
process(clk, reset)
begin
--f I1=0=>I1=1
if(I1='1')and (cpt1=0)then
Top_Tour_T1<='1';
cpt1<=1;
--begin the counter 330000 pour 660us
elsif(cpt1>0)and (cpt1<33000)then
cpt1<=cpt1+1;
--after 660us, top disappear
elsif(cpt1>=33000)then
cpt1<=cpt1+1;
if(I1='0') then
cpt1<=0;
end if;
Top_Tour_T1<='0';
end if;
end if;
end process;
end architecture behavior;
------解决思路----------------------
描述问题的时候说详细些
仿真没出现这样的问题？如果方波间隔小于660us你想要怎么样的输出？你的CLK是50M？方波的频率范围是多少？
------解决思路----------------------
signaltap 查查呗
------解决思路----------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.ALL;
ENTITY top_sensor IS
PORT
(
-- Input ports
rst : in std_logic;
clk : in std_logic; --50MHZ
pulse_in : in std_logic;
-- Output ports
pulse_out : out std_logic --! Top round sensor 1 out
);
END top_sensor;
ARCHITECTURE arc OF top_sensor IS
--ref signals
signal pulse_in_d1:std_logic:='0';
signal pulse_in_d2:std_logic:='0';
signal start_sig:std_logic:='0';
signal cnt_660us:std_logic_vector(15 downto 0):=(others=>'0');
BEGIN
process(rst,clk)
begin
if rst='1' then
pulse_in_d1<='0';
pulse_in_d2<='0';
start_sig<='0';
elsif rising_edge(clk) then
pulse_in_d1<=pulse_in;
pulse_in_d2<=pulse_in_d1;
if (pulse_in_d2='0') and (pulse_in_d1='1') then
start_sig<='1';
elsif (cnt_660us>="1000000011101000") then
start_sig<='0';
end if;
end if;
end process;
process(rst,clk)
begin
if rst='1' then
cnt_660us<=(others=>'0');
pulse_out<='0';
elsif rising_edge(clk) then
if (cnt_660us>="1000000011101000") then
cnt_660us<=(others=>'0');
pulse_out<='0';
elsif start_sig='1' then
cnt_660us<=cnt_660us+'1';
pulse_out<='1';
end if;
end if;
end process;
END arc;