(Verilog)Moore和Mealy型有限状态机(FSM)实现序列检测(10010)

Moore和Moore型状态机区别：

Moore型：

    1. 输出只与当前状态有关；

    2. 所需状态数较多，响应速度慢

Mealy型：

    1. 输出与当前状态和当前输入有关；

    2. 所需状态数较少，响应速度快

用Moore型有限状态机实现序列10010的检测：

Verilog程序：

module seq_10010_Moore(input   wire    clk,input   wire    rst_n,input   wire    data_in,output  reg     out);reg [2:0] state, state_next;parameter  IDLE = 3'd0,S1 = 3'd1,S2 = 3'd2,S3 = 3'd3,S4 = 3'd4,S5 = 3'd5;always@(posedge clk or negedge rst_n)if(!rst_n)state <= IDLE;elsestate <= state_next;always@(data_in or state)case(state)IDLE:state_next = (data_in) ? S1:IDLE;S1:state_next = (data_in) ? S1:S2;S2:state_next = (data_in) ? S1:S3;S3:state_next = (data_in) ? S4:IDLE;S4:state_next = (data_in) ? S1:S5;S5:state_next = (data_in) ? S1:S3;default: state_next = IDLE;endcasealways@(*)if(!rst_n)out = 0;else if(state == S5)out = 1;elseout = 0;endmodule

RTL视图：输出与输入无关

testbench:

`timescale 1ns / 1psmodule tb_seq_10010_Moore();
reg    clk;
reg    rst_n;
reg    data_in;wire     out;initial beginclk = 0;rst_n = 0;data_in = 0;#20 rst_n = 1;#20 data_in = 0;#70 data_in = 1;#20 data_in = 0;#20 data_in = 1;#20 data_in = 0;#20 data_in = 0;#20 data_in = 1;#20 data_in = 0;#20 data_in = 0;#20 data_in = 1;#20 data_in = 0;#20 data_in = 0;#20 data_in = 0;#20 data_in = 1;#20 data_in = 0;#20 data_in = 0;
endalways #10 clk = ~clk;seq_10010_Moore seq_10010_Moore_inst
(.clk      ( clk      ),.rst_n    ( rst_n    ),.data_in  ( data_in  ),.out      ( out      )
);endmodule

逻辑仿真结果：

用Mealy型有限状态机实现序列10010的检测：

Verilog程序：

module seq_10010_Mealy(input   wire    clk,input   wire    rst_n,input   wire    data_in,output  reg     out);reg [2:0] state, state_next;parameter  IDLE = 3'd0,S1 = 3'd1,S2 = 3'd2,S3 = 3'd3,S4 = 3'd4;always@(posedge clk or negedge rst_n)if(!rst_n)state <= IDLE;elsestate <= state_next;always@(data_in or state)case(state)IDLE:state_next = (data_in) ? S1:IDLE;S1:state_next = (data_in) ? S1:S2;S2:state_next = (data_in) ? S1:S3;S3:state_next = (data_in) ? S4:IDLE;S4:state_next = (data_in) ? S1:S2;default: state_next = IDLE;endcasealways@(posedge clk or negedge rst_n)if(!rst_n)out <= 0;else if(state == S4 && ~data_in)out <= 1;elseout <= 0;endmodule

RTL视图：输出与输入有关

testbench:

`timescale 1ns / 1psmodule tb_seq_10010_Mealy();
reg    clk;
reg    rst_n;
reg    data_in;wire   out;initial beginclk = 0;rst_n = 0;data_in = 0;#20 rst_n = 1;#20 data_in = 0;#60 data_in = 1;#20 data_in = 0;#20 data_in = 1;#20 data_in = 0;#20 data_in = 0;#20 data_in = 1;#20 data_in = 0;#20 data_in = 0;#20 data_in = 1;#20 data_in = 0;#20 data_in = 0;#20 data_in = 0;#20 data_in = 1;#20 data_in = 0;#20 data_in = 0;
endalways #10 clk = ~clk;seq_10010_Mealy seq_10010_Mealy_inst
(.clk      ( clk      ),.rst_n    ( rst_n    ),.data_in  ( data_in  ),.out      ( out      )
);endmodule

逻辑仿真结果：