[DRC UCIO-1] Unconstrained Logical Port: 6 out of 12 logical ports have no user assigned specific

vivado2018.3 在调试cameralink接口时，synthesis 和implement都过了，但生成bit文件时报如下错误

[DRC UCIO-1] Unconstrained Logical Port: 6 out of 12 logical ports have no user assigned specific
location constraint (LOC). This may cause I/O contention or incompatibility with the board power 
or connectivity affecting performance, signal integrity or in extreme cases cause damage to the
device or the components to which it is connected. To correct this violation, specify all pin
locations. This design will fail to generate a bitstream unless all logical ports have a user 
specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations
(not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  
NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command
to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. 
Problem ports: CL1_Xn[3], CL1_Xn[2], CL1_Xn[0], CL1_Xp[3], CL1_Xp[2], and CL1_Xp[0].

根据里面的提示，要加入命令set_property SEVERITY {Warning} [get_drc_checks UCIO-1]才行

于是根据参考

https://blog.csdn.net/qq_41634276/article/details/82750794

https://china.xilinx.com/support/answers/56354.html

我也新建了记事本，里面只加了下面这句话

set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

然后做成.tcl文件 加入到bitstreams settings指定位置，然后重新综合编译最后不报错了。

我这里报这个错误的原因是这个cameralink接口原始是当作接收端用的，但现在需要把它变成发送端以后，物理端口的管脚要重新分配的。所以根据下图和原理图重新分配了管脚。这样重新分配后可能硬件做了检测防止出现烧坏端口的情况，所以不让通过。