verilog实现鼠标协议PS/2 mouse protocol

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原博客链接：https://blog.csdn.net/qq_38305370
原博主昵称：城外南风起
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packet parser

原题目：

The PS/2 mouse protocol sends messages that are three bytes long. However, within a continuous byte stream, it’s not obvious where messages start and end. The only indication is that the first byte of each three byte message always has bit[3]=1 (but bit[3] of the other two bytes may be 1 or 0 depending on data).

We want a finite state machine that will search for message boundaries when given an input byte stream. The algorithm we’ll use is to discard bytes until we see one with bit[3]=1. We then assume that this is byte 1 of a message, and signal the receipt of a message once all 3 bytes have been received (done).

The FSM should signal done in the cycle immediately after the third byte of each message was successfully received.

波形demo：

这道题的状态机可以用下图描述：

这道题的难点是：正常状态（没有error）下，DONE状态和BYTE1状态的时段重合的；异常状态（有error）下，DONE状态和BYTE1状态是不重合的，而且会在DONE状态和BYTE1状态的时段中间会多出一个ERROR状态。

但其实，可以认为BYTE1状态其实就是ERROR状态，直到in[3]==1，才转为BYTE2状态，BYTE2状态前一个周期的ERROR状态自动转换为BYTE1状态。

实现代码：

module top_module(input clk,input [7:0] in,input reset,    // Synchronous resetoutput done); //parameter DONE = 2'b00, BYTE1 = 2'b01, BYTE2 = 2'b10, BYTE3 = 2'b11;reg [1:0] state, next_state;// State transition logic (combinational)always @(*) begin// State transition logiccase(state)BYTE1: next_state = in[3] ? BYTE2 : BYTE1;BYTE2: next_state = BYTE3;BYTE3: next_state = DONE;DONE: next_state = in[3] ? BYTE2 : BYTE1;            default: next_state = BYTE1;endcaseend// State flip-flops (sequential)always @(posedge clk) beginif(reset) beginstate <= BYTE1;endelse beginstate <= next_state;endend// Output logicassign done = (state == DONE);endmodule

packet parser and datapath

原题目：

Now that you have a state machine that will identify three-byte messages in a PS/2 byte stream, add a datapath that will also output the 24-bit (3 byte) message whenever a packet is received (out_bytes[23:16] is the first byte, out_bytes[15:8] is the second byte, etc.).

out_bytes needs to be valid whenever the done signal is asserted. You may output anything at other times (i.e., don’t-care).

波形demo：

在packet parser代码的基础上补充上输出赋值即可。利用三个8位reg变量byte1, byte2, byte3分别储存三个byte。需要注意的是，byte1, byte2, byte3赋值需在时序逻辑中，才能保证储存的是上升沿时刻的in（in在一个周期内可以多次变化）。此外，如果在组合逻辑中赋值，在输出out_bytes时，前一条消息的byte1会被当前消息的byte1覆盖掉。

实现代码：

module top_module(input clk,input [7:0] in,input reset,    // Synchronous resetoutput [23:0] out_bytes,output done); //parameter DONE = 2'b00, BYTE1 = 2'b01, BYTE2 = 2'b10, BYTE3 = 2'b11;reg [1:0] state, next_state;reg [7:0] byte1, byte2, byte3;// State transition logic (combinational)always @(*) begin// State transition logiccase(state)BYTE1: next_state = in[3] ? BYTE2 : BYTE1;BYTE2: next_state = BYTE3;BYTE3: next_state = DONE;DONE: next_state = in[3] ? BYTE2 : BYTE1;            default: next_state = BYTE1;endcaseend// State flip-flops (sequential)always @(posedge clk) beginif(reset) beginstate <= BYTE1;endelse begin            case(state)BYTE1: byte1 <= in;BYTE2: byte2 <= in;BYTE3: byte3 <= in;DONE: byte1 <= in;default: byte1 <= in;endcasestate <= next_state;endend// Output logicassign done = (state == DONE);assign out_bytes = {byte1, byte2, byte3};endmodule

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