目录
序言
原题复现
设计1
设计2
最后一句话
序言
这篇博客的标题起的，好像就是为独热码而讨论的，其实不然，下面给出一个题目，用任何方式的状态编码都可以，但是我就想讨论下用独热码来实现。
一种写法是上篇博客写的那样，用简单的方式实现状态转移。
原题复现
先给出原题：
The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include an asynchronous reset that resets the FSM to state A.
| State | Next state | Output | |
|---|---|---|---|
| in=0 | in=1 | ||
| A | A | B | 0 |
| B | C | B | 0 |
| C | A | D | 0 |
| D | C | B | 1 |
Module Declaration
module top_module(input clk,input in,input areset,output out); 设计1
读过上篇博客肯定知道我为什么这么写：
module top_module(input clk,input in,input areset,output out); //parameter A = 4'b0001, B = 4'b0010, C = 4'b0100, D = 4'b1000;reg [3:0] state = 0;wire [3:0] next_state;// State transition logicassign next_state[0] = state[0]&(in == 0) | state[2] & (in == 0);assign next_state[1] = state[0]&in | state[1]&in | state[3]∈assign next_state[2] = state[1]&(in == 0) | state[3]&(in == 0);assign next_state[3] = state[2] & in;// State flip-flops with asynchronous resetalways@(posedge clk or posedge areset) beginif(areset) state <= A;else state <= next_state;end// Output logicassign out = (state[3]) ? 1 : 0;endmodule
算了，纯属zb，以后也不怎么会用了。
设计2
给出最正常的三段式吧：
module top_module(input clk,input in,input areset,output out); //parameter A = 4'b0001, B = 4'b0010, C = 4'b0100, D = 4'b1000;reg [3:0] state, next_state;// State transition logicalways@(*) begincase(state)A: beginif(in == 0) next_state = A;else next_state = B;endB: beginif(in == 0) next_state = C;else next_state = B;endC: beginif(in == 0) next_state = A;else next_state = D;endD: beginif(in == 0) next_state = C;else next_state = B;endendcaseend// State flip-flops with asynchronous resetalways@(posedge clk or posedge areset) beginif(areset) state <= A;else state <= next_state;end// Output logicassign out = (state == D) ? 1 : 0;endmodule
最后一句话
事实上，这个系列的作者用的思考都是设计1。