目录
背景
原题复现
我的方案
状态转移图
我的设计
更新方案
FPGA/IC群推荐
背景
这是这个系列中的一个状态机的题目，但是相比于给了你完整状态转移图之类的题目，这个题目还是稍微有点难的，我实在不知道该怎么给这个博客起个什么名字？
我在线等一个简单的方式去解决今天的问题，而如题所说，我用最无能的方式来解决这个问题，但简单的方式一定存在。
2019/12/16更新
今天一个帅兄弟给了我一个答案，很巧妙，这里十分感谢。我把它放到后面来给出。
原题复现
原题复现：
Consider a finite state machine with inputs s and w. Assume that the FSM begins in a reset state called A, as depicted below. The FSM remains in state A as long as s = 0, and it moves to state B when s = 1. Once in state B the FSM examines the value of the input w in the next three clock cycles. If w = 1 in exactly two of these clock cycles, then the FSM has to set an output z to 1 in the following clock cycle. Otherwise z has to be 0. The FSM continues checking w for the next three clock cycles, and so on. The timing diagram below illustrates the required values of z for different values of w.
Use as few states as possible. Note that the s input is used only in state A, so you need to consider just the w input.
我的方案
状态转移图
我的解决方案，有点无奈，多加了一些状态：
我的设计
根据此状态转移图给出我的设计：
module top_module (input clk,input reset, // Synchronous resetinput s,input w,output z
);localparam A = 0, B = 1, S0 = 3, S1 = 4, S2 = 5, S3 = 6, S4 = 7, S5 = 8, S6 = 9, S7 = 10, S8 = 11, S9 = 12, S10 = 13, S11 = 14;reg [3:0] state, next_state;always@(*) begincase(state)A: beginif(s) next_state = B;else next_state = A;endB: beginif(w) next_state = S1;else next_state = S0;endS0: beginif(w) next_state = S2;else next_state = S4;endS1: beginif(w) next_state = S9;else next_state = S6;endS2: beginif(w) next_state = S3;else next_state = S5;endS3: beginif(w) next_state = S1;else next_state = S0;endS4: beginnext_state = S5;endS5: beginif(w) next_state = S1;else next_state = S0;endS6: beginif(w) next_state = S7;else next_state = S8;endS7: beginif(w) next_state = S1;else next_state = S0;endS8: beginif(w) next_state = S1;else next_state = S0;endS9: beginif(w) next_state = S11;else next_state = S10;endS10: beginif(w) next_state = S1;else next_state = S0;endS11: beginif(w) next_state = S1;else next_state = S0;enddefault: beginnext_state = A;endendcaseendalways@(posedge clk) beginif(reset) state <= 0;else state <= next_state;endassign z = (state == S10 || state == S7 || state == S3) ? 1 : 0;endmodule
测试成功。
更新方案
今天群里的大佬给了一种简单的方法，状态转移图确实简单了，但是理解起来呢？
我之前用的方案是在B之后的三个周期内，列举w的值，取值情况有8种，然后添加更多的状态去解决这个问题，不得不说状态转移图看起来复杂很多，也绝对不是推荐的方案。
我等待的确实是今天的这个方案，通过计数，不需要添加更多的状态，这也是我一开始就想用的方法，只是计数的时序当时没有搞定，今天很感谢，群里的一位兄弟。
直接给出设计，通过代码就应该能看出来设计的思路：
module top_module (input clk,input reset, // Synchronous resetinput s,input w,output z
);parameter A = 1'b0, B = 1'b1;reg current_state;reg next_state;always@(posedge clk)beginif(reset)begincurrent_state <= A;endelse begincurrent_state <= next_state;endendalways@(*)begincase(current_state)A:beginnext_state = s ? B : A;endB:beginnext_state = B;endendcaseendreg w_reg1;reg w_reg2;always@(posedge clk)beginif(reset)beginw_reg1 <= 1'b0;w_reg2 <= 1'b0;endelse if(next_state == B)beginw_reg1 <= w;w_reg2 <= w_reg1;endelse beginw_reg1 <= 1'b0;w_reg2 <= 1'b0;endendalways@(posedge clk)beginif(reset)beginz <= 1'b0;endelse if(next_state == B && counter == 2'd0)beginif(~w & w_reg1 & w_reg2 | w & ~w_reg1 & w_reg2 | w & w_reg1 & ~w_reg2)beginz <= 1'b1;endelse beginz <= 1'b0;endendelse beginz <= 1'b0;endend reg [1:0] counter;always@(posedge clk)beginif(reset)begincounter <= 2'd0;endelse if(counter == 2'd2)begincounter <= 2'd0;endelse if(next_state == B)begincounter <= counter + 1'b1;endendendmodule巧妙之处在于将输入w延迟两拍之后进行判断，如果有两个w为1，则在下一个周期将输出z置位.
有的朋友，也许在状态机的设计中，习惯将第三段使用组合逻辑来实现，这个题目的第三段也可以使用组合逻辑，但是呢？确实也没有必要，因为状态机的第三段本身既可以使用组合逻辑，也可以使用时序逻辑，如果使用时序逻辑。
下面给出组合逻辑的方案：
module top_module (input clk,input reset, // Synchronous resetinput s,input w,output reg z
);parameter A = 1'b0, B = 1'b1;reg current_state;reg next_state;always@(posedge clk)beginif(reset)begincurrent_state <= A;endelse begincurrent_state <= next_state;endendalways@(*)begincase(current_state)A:beginnext_state = s ? B : A;endB:beginnext_state = B;endendcaseendreg w_reg1;reg w_reg2;always@(posedge clk)beginif(reset)beginw_reg1 <= 1'b0;w_reg2 <= 1'b0;endelse if(next_state == B)beginw_reg1 <= w;w_reg2 <= w_reg1;endelse beginw_reg1 <= 1'b0;w_reg2 <= 1'b0;endendreg z_mid;always@(*)beginif(reset)beginz_mid <= 1'b0;endelse if(current_state == B && counter == 2'd0)beginif(~w & w_reg1 & w_reg2 | w & ~w_reg1 & w_reg2 | w & w_reg1 & ~w_reg2)beginz_mid <= 1'b1;endelse beginz_mid <= 1'b0;endendelse beginz_mid <= 1'b0;endendalways@(posedge clk)beginif(reset)beginz <= 1'b0;endelse beginz <= z_mid;endendreg [1:0] counter;always@(posedge clk)beginif(reset)begincounter <= 2'd0;endelse if(counter == 2'd2)begincounter <= 2'd0;endelse if(next_state == B)begincounter <= counter + 1'b1;endendendmodule只需要将第三段改为组合逻辑，但是输出需要延迟一拍，为什么？看时序图。
FPGA/IC群推荐
IC/FPGA 技术交流
有幸在这个群里认识了诸多俊杰，让我欣慰。