libero编译错误之port name doesn‘t exist inthe netlist or is not connected to an IoCell macro at PDC line

使用三模工具得到的*.edf网表文件在Libero环境下的Designer进行编译和布线时出现错误，port name doesn’t exist inthe netlist or is not connected to an IoCell macro at PDC line，搜寻了很多答案，最终link解释了原因，虽然问题相同，工具不同，但是按照这个解释，可以完美解决这个问题。
解释如下：
Synplicity v7.7 or older version uses ( ) in renaming of bus signals (for VHDL flow). In Synplicity v8.2B and later versions, the bus renaming uses square brackets [ ].

    Synplify v7.7 (Libero v6.2)cell count8_behave (cellType GENERIC)(view behavioral (viewType NETLIST)(interface(port (array (rename q "Q(7:0)") 8) (direction OUTPUT))Synplify v8.2B (Libero v6.3)(cell count8_behave (cellType GENERIC)(view behavioral (viewType NETLIST)(interface(port (array (rename q "Q[7:0]") 8) (direction OUTPUT))If you use an existing PDC with following assignment in Libero v6.3:

set_io Q(7) -pinname 85 -fixed yes
set_io Q(6) -pinname 92 -fixed yes
This port name change results in failure to set constraints. This will happen with both GCF and PDC constraints.
In addition, if you turn off the abort on error option as shown below, the I/Os may be arbitrarily reassigned to different pins.
解决办法：
The Synplicity naming convention will not be fixed to support constraint settings in GCF and PDC files. User needs to manually change their constraint file to match the Synplify bus naming convention.
In GCF
set_io Q[7] -pinname 85 -fixed yes
set_io Q[6] -pinname 92 -fixed yes
In PDC
set_io Q \ [7 \ ] -pinname 85 -fixed yes
set_io Q \ [6 \ ] -pinname 92 -fixed yes
官网推荐将()改为[],但是在本次遇到的问题上，因为edf文件里用的是()，不方便再次综合，而io.pdc约束文件里使用[],导致找不到对应管脚，所以把PDC文件里的将[]改为全部改为了(),编译通过！