AREA Init, CODE, READONLY
CODE32
; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
NO_INT EQU 0xC0 ; Mask used to disable interrupts (Both FIR and IRQ)
ENABLE_INT EQU 0x3f ; enable IRQ and FIQ interrupt
Len_FIQ_Stack EQU 0x800
Len_IRQ_Stack EQU 0x800
Len_ABT_Stack EQU 0x100
Len_UND_Stack EQU 0x100
Len_SVC_Stack EQU 0x800 ;this is Pseudotarget
top_of_stacks EQU 0x00300000
; Add lengths > 0 for FIQ_Stack, ABT_Stack, UND_Stack if you need them.
; Offsets will be loaded as immediate values.
; Offsets must be 8 byte aligned.
;TOP_Stack_Addr EQU 0x00300000
Offset_FIQ_Stack EQU 0x100
Offset_IRQ_Stack EQU Offset_FIQ_Stack + Len_FIQ_Stack
Offset_ABT_Stack EQU Offset_IRQ_Stack + Len_IRQ_Stack
Offset_UND_Stack EQU Offset_ABT_Stack + Len_ABT_Stack